1. Field of the Invention
The present invention relates in general to the field of data processing. In one aspect, the present invention relates to a method and system for reducing power consumption in a wireless communications device.
2. Description of the Related Art
In general, data processors are capable of executing a variety of instructions. Processors are used in a variety of applications, including communication systems formed with wireless and/or wire-lined communication devices. Such communication systems range from national and/or international cellular telephone systems to the Internet to point-to-point in-home wireless networks. Each type of communication system is constructed, and hence operates, in accordance with one or more communication standards. For instance, wireless communication systems may operate in accordance with one or more standards including, but not limited to, IEEE 802.11, Bluetooth, advanced mobile phone services (AMPS), digital amps, global system for mobile communications (GSM), code division multiple access (CDMA), local multi-point distribution systems (LMDS), multi-channel-multi-point distribution systems (MMDS) and/or variations thereof.
Especially with wireless and/or mobile communication devices (such as a cellular telephone, two-way radio, personal digital assistant (PDA), laptop computer, home entertainment equipment, etc.), the processor or processors in a device must be able to run various complex communication programs using only a limited amount of power that is provided by power supplies, such as batteries, contained within such devices.
For example, for a wireless communication device to participate in wireless communications, the device includes a built-in radio transceiver (i.e., receiver and transmitter) or is coupled to an associated radio transceiver (e.g., a station for in-home and/or in-building wireless communication networks, RF modem, etc.). To implement the transceiver function, a transmitter is provided which typically includes a data modulation stage, one or more intermediate frequency (IF) stages and a power amplifier. The data modulation stage converts raw data into baseband signals in accordance with a particular wireless communication standard. The intermediate frequency stages mix the baseband signals with one or more local oscillations to produce RF signals. The power amplifier amplifies the RF signals prior to transmission via an antenna. In addition, one or more processors and other modules are used to form a receiver which is typically coupled to an antenna and includes a low noise amplifier, one or more intermediate frequency stages, a filtering stage and a data recovery stage. The low noise amplifier receives inbound RF signals via the antenna and amplifies them. The intermediate frequency stages mix the amplified RF signals with one or more local oscillations to convert the amplified RF signal into baseband signals or intermediate frequency signals. The filtering stage filters the baseband signals or the intermediate frequency (IF) signals to attenuate unwanted out-of-band signals to produce filtered signals. The data recovery stage recovers raw data from the filtered signals in accordance with the particular wireless communication standard.
Because of the computational intensity (and the associated power consumption by the processor(s)) for communications transceiver functions, it is an important goal in the design of wireless and/or mobile communication devices to minimize processor and other module operations (and the associated power consumption). It is particularly crucial for mobile applications in order to extend battery life. With conventional solutions for saving power, a variety of complex circuit and hardware designs have been proposed. These mechanisms typically implement CPU clock management by switching between an active mode and an idle mode. In the idle mode, the processor has no work to do and the CPU stops its clocking and waits for an interrupt or uses a predetermined and fixed sleep interval to periodically power-up to check for work activity. In the active mode, the CPU resumes its maximum pre-configured clock speed. These approaches do not provide sufficient flexibility to maximize power savings to the extent that may be desired. Nor do these approaches provide for power management that responds to user-related activity to adjust power consumption. In addition, the interrupt-based approach can result in substantial latencies for entering and leaving the idle mode, which restricts the power that can be saved and the range of applicability because these latencies may preclude a processor from being able to deactivate modules before having to reactivate them. Indeed, many interrupt-based implementations are based on complex signaling mechanisms and processor state transitions which require significant hardware and software support and also exhibit long latencies.
In addition to the complexity of the computational requirements for a communications transceiver, such as described above, the ever-increasing need for higher speed communications systems imposes additional performance requirements and resulting costs for communications systems. In order to reduce costs, communications systems are increasingly implemented using Very Large Scale Integration (VLSI) techniques. The level of integration of communications systems is constantly increasing to take advantage of advances in integrated circuit manufacturing technology and the resulting cost reductions. This means that communications systems of higher and higher complexity are being implemented in a smaller and smaller number of integrated circuits. For reasons of cost and density of integration, the preferred technology is CMOS. To this end, digital signal processing (“DSP”) techniques generally allow higher levels of complexity and easier scaling to finer geometry technologies than analog techniques, as well as superior testability and manufacturability.
Therefore, a need exists for a method and apparatus that provides reduced power consumption. In addition, a need exists for reducing power consumption without requiring complex hardware and elaborate signaling mechanisms. Moreover, a need exists for improved selectivity when determining the nature and extent of the required power-up operations. There is also a need for a better system that is capable of performing the above functions and overcoming these difficulties without increasing circuit area and operational power. Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.